Integrated circuits are typically packaged in hermetically sealed containers to prevent contamination which could disrupt the operation of their integrated circuit dies. These containers are known in the industry as "chip carriers."
Chip carriers are typically constructed from several component parts. The largest part is usually a plastic or ceramic base known as a "substrate." Additionally, the assignee of the present invention contemplates the use of silicon as a substrate material for the present invention. The substrate will usually have a cavity formed at its center to hold the integrated circuit die of the completed integrated circuit.
To transmit signal and power to and from the die conductive leads extending from beyond the outer periphery of the substrate to the interior of the chip carrier near the cavity are mounted on the substrate. The portion of the conductive leads extending beyond the substrate will be used to connect the integrated circuit to external circuitry. The end of the conductive leads near the cavity will have bonding wires attached to them that connect to bonding pads on the integrated circuit die. Thus, the conductive leads and bonding wires allow access to the die in the finished integrated circuit. Conductive leads are usually manufactured as a single part known in the industry as a "leadframe." A leadframe allows all of leads to be handled as a single component during assembly of the chip carrier.
Assembling of a typical chip carrier begins with the deposition of an adhesive glass layer on the surface of the substrate. The leadframe is then placed on the adhesive glass into which it becomes partially imbedded and thus attached to the substrate. Finally, a layer of sealing glass is deposited, from the outer periphery of the substrate inward, over the leadframe wires . The sealing glass will provide the hermetic seal required in the completed integrated circuit device.
The typical chip carrier is now assembled and ready to be used in the packaging of an integrated circuit. First, an integrated circuit die is attached in the cavity to the substrate. Next, the integrated circuit die is electrically connected by conductive wires, known in the industry as "bondwires," to the leadframe leads. The bondwires are typically attached ultrasonically or by thermocompression, one end to a pad on the integrated circuit die; the other to a part of the leadframe lead near the cavity. Next, a lid is placed over the chip carrier sealing glass. Finally, the package is heated sufficiently to melt the chip carrier sealing glass, but not the adhesive glass which has a higher melting point than the sealing glass. The melted sealing glass cools and forms a hermetic seal on the now packaged integrated circuit device.
While the above packaging scheme has been highly successful, the need by industry for increasingly fast and complex integrated circuits runs up against limitations in the above packaging scheme. To meet the requirements of faster and more complex integrated circuits, both the component density and need for communication points with the integrated circuit have increased. An example of a need for faster and more complex integrated circuits are modern super-computers, such as those manufactured by Cray Research, Inc., the assignee of the present invention.
More communication points require both more chip carrier leads and more pads on the integrated circuit die. Faster integrated circuits generally require that integrated circuit elements; transistors, resistors, etc, be as small as possible and that the distances between elements be minimized, resulting in an integrated circuit die with a small surface area. Since it is required in high speed circuits to minimize distances, the leads of a lead frame converge toward the die. The result is that more leads are located in a small area causing a decrease in spacing between the leads.
Unfortunately, a decreased spacing between the leads increases the capacitance between the leads. This interlead capacitance adversely affects the quality of signals transmitted on the leads of the leadframe by increasing: signal rise times and fall times; increasing signal reflections; causing greater impedance mismatches; increasing signal termination problems; creating a decrease in signal propagation velocity, and a coupling of signals between adjacent leads.
At very high speeds the proper termination of all transmission lines becomes important. Proper termination of an integrated circuit requires that the interlead capacitance be both accurately known and stable so that an effective termination can be designed and implemented. The above mentioned packaging scheme does not give the accurate and stable interlead capacitance required because the interlead dielectric constant depends on uncontrolled variables such as the length of the lead over the adhesive glass, the extent that the lead imbeds in the adhesive glass, the length of the lead under the sealing glass, and the extent that the sealing glass melts and flows between adjacent leads.
Typical prior art chip carrier specifications include allowable amounts of glass overflow and pullback. Glass overflow refers to glass flow down the edge of the substrate or wicking along the leads while glass pullback refers to concavities formed in the glass between the lead and the substrate or between the lead and the lid. Tight tolerances of glass overflow and pullback are difficult to meet using the prior art because of the thickness of the glass layers used.
Glass overflow is a problem because it causes glass chips when the overflow breaks off. Glass chips cause problems during plating of the leads, testing of the devices, and during assembly of the completed integrated circuit onto a circuit board. Additionally, if glass chips are formed at the inner cavity of the chip carrier the glass may be retained in the cavity and cause problems when attaching bondwires to the integrated circuit die or when attaching the die to the substrate. Glass pullback causes problems when plating the leads by inducing the plating to produce lead-to-lead shorts.
A major concern when interconnecting an integrated circuit die with the chip carrier leads is the quality of the wirebond at the leads. To obtain consistent bond quality all leads must be completely supported and highly coplanar since the bondwire tool places a compression force on the lead and is set to operate in a fixed plane. If a lead is much lower than its neighbors the resulting bond will be weak and pull-of. If the lead is much higher the bonding wire will be squashed into the lead and cause a break at the toe of the bond. If the lead is not completely supported when the wirebond tool comes down to attach the bonding wire the lead will flex and create a poor wirebond.
There is therefore a need for an integrated circuit chip carrier with closely spaced leadframe leads that permits interlead capacitance to be low, stable and accurately known; reduces the amount of glass chips caused by handling; and assists the formation of consistent quality wirebonds at the leads.